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XR-2207
...the analog plus company TM
Voltage-Controlled Oscillator
June 1997-3
FEATURES D Excellent Temperature Stability (20ppm/C) D Linear Frequency Sweep D Adjustable Duty Cycle (0.1% to 99.9%) D Two or Four Level FSK Capability D Wide Sweep Range (1000:1 Minimum) D Logic Compatible Input and Output Levels D Wide Supply Voltage Range ($4V to $13V) D Low Supply Sensitivity (0.1% /V) D Wide Frequency Range (0.01Hz to 1MHz) D Simultaneous Triangle and Squarewave Outputs GENERAL DESCRIPTION The XR-2207 is a monolithic voltage-controlled oscillator (VCO) integrated circuit featuring excellent frequency stability and a wide tuning range. The circuit provides simultaneous triangle and squarewave outputs over a frequency range of 0.01Hz to 1MHz. It is ideally suited for FM, FSK, and sweep or tone generation, as well as for phase-locked loop applications. ORDERING INFORMATION
Part No. XR-2207M XR-2207CP XR-2207D XR-2207ID
APPLICATIONS D FSK Generation D Voltage and Current-to-Frequency Conversion D Stable Phase-Locked Loop D Waveform Generation - Triangle, Sawtooth, Pulse, Squarewave D FM and Sweep Generation
The XR-2207 has a typical drift specification of 20ppm/C. The oscillator frequency can be linearly swept over a 1000:1 range with an external control voltage; and the duty cycle of both the triangle and the squarewave outputs can be varied from 0.1% to 99.9% to generate stable pulse and sawtooth waveforms.
Package 14 Lead 300 Mil CDIP 14 Lead 300 Mil PDIP 16 Lead 300 Mil JEDEC SOIC 16 Lead 300 Mil JEDEC SOIC
Operating Temperature Range -55C to +125C 0C to +70C 0C to +70C -40C to +85C
BLOCK DIAGRAM
C1 C1 R1 R2 R3 R4
2 3
VCC GND
1 10
BIAS
11 A1 14 13 A2 12
Timing Capacitor
4 5 6 7
Timing Resistors
Rev. 2.02
E1975
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z FAX (510) 668-7017 1
I I I
TWO SWO VEE BKI2 BKI1
Triangle Wave Out Square Wave Out
VCO
Current Switches
9 8
Binary Keying Inputs
Figure 1. Block Diagram
XR-2207
PIN CONFIGURATION
VCC C1 C2 R1 R2 R3 R4 BKI1
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
VCC C1 C2 R1 R2 R3 R4
1 2 3 4 5 6 7
14 13 12 11 10 9 8
TWO SWO VEE BIAS GND BKI2 BKI1
NC NC TWO SWO VEE BIAS GND BKI2
14 Lead PDIP, CDIP (0.300")
16 Lead SOIC (Jedec, 0.300")
PIN DESCRIPTION
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15, 16 Symbol VCC C1 C2 R1 R2 R3 R4 BKI1 BKI2 GND BIAS VEE SWO TWO NC O O I I I I I I I I I Type Description Positive Power Supply. Timing Capacitor Input. Timing Capacitor Input. Timing Resistor 1 Input. Timing Resistor 2 Input. Timing Resistor 3 Input. Timing Resistor 4 Input. Binary Keying 1 Timing Resistor Select Input. Binary Keying 2 Timing Resistor Select Input. Ground Pin. Bias Input for Single Supply Operation. Negative Power Supply. Square Wave Output Signal. Triangle Wave Output Signal. Only SOIC-16 Package.
Rev. 2.02 2
XR-2207
ELECTRICAL CHARACTERISTICS
Test Conditions: Test Circuit of Figure 3 and Figure 4, VCC = VEE = 6V, TA = +25C, C = 5000pF, R1 = R2 = R3 = R4 = 20k, RL = 4.7k, Binary Inputs Grounded, S1 and S2 Closed Unless Otherwise Specified
XR-2207ID/XR-2207M Parameters General Characteristics Supply Voltage Single Supply S li Supplies Split S li Supply Current Single Supply Split Supply Positive Negative 5 4 7 6 5 4 8 7 mA mA 5 7 5 8 mA 8 $4 26 $13 8 $4 26 $13 V V See Figure 3 See Figure 4 See Figure 3 Measure at Pin 1, S1, S2 Open See Figure 4 Measure at Pin 1, S1, S2 Open Measured at Pin 12, S1, S2 Open Min. Typ. Max. XR-2207CP/D Min. Typ. Max. Units Conditions
Oscillator Section - Frequency Characteristics Upper Frequency Limit Lowest Practical Frequency Frequency Accuracy Frequency Matching Frequency Stability Temperature P Power S Supply l Sweep Range Sweep Linearity 10:1 Sweep 1000:1 Sweep S FM Distortion Recommended Range of Timing Resistors Impedance at Timing Pins DC Level at Timing Terminals Binary Keying Inputs Switching Threshold Input Impedance 1.4 2.2 5 2.8 1.4 2.2 5 2.8 V k Measured at Pins 8 and 9, Referenced to Pin 10 1.5 75 10 1 5 0.1 2000 1.5 75 10 2 1.5 5 0.1 2000 % k mV 20 0.15 1000:1 3000:1 50 30 0.15 1000:1 ppm/C %V fH/fL % R3 = 1.5k for fH1 R3 = 2M for fL C =5000pF fH=10kHz, fL= 1kHz fH=100kHz, fL= 100Hz $10% FM Deviation See Characteristic Curves Measured at Pins 4, 5, 6, or 7 0C < TA< 70C 0.5 1.0 0.01 $1 0.5 $3 0.5 1.0 0.01 $1 0.5 $5 MHz Hz % of fO % of fO C =500pF, R3 = 2k C =50F, R3 = 2M
Notes Bold face parameters are covered by production test and guaranteed over operating temperature range.
Rev. 2.02 3
XR-2207
ELECTRICAL CHARACTERISTICS (CONT'D)
XR-2207ID/XR-2207M Parameters Output Characteristics Triangle Output Amplitude Impedance I d DC Level L l Linearity Squarewave Output Amplitude Saturation Voltage Rise Time Fall Time 11 12 0.2 200 20 0.4 11 4 6 10 +100 0.1 4 Min. Typ. Max.
XR-2207CP/D Min. Typ. Max. Units Conditions
Measured at Pin 13 6 10 +100 0.1 VPP mV % Referenced to Pin 10 From 10% to 90% to Swing Measured at Pin 13, S2 Closed 12 0.2 200 20 0.4 Vpp V nsec nsec Referenced to Pin 12 CL 10pF CL 10pF
Notes Bold face parameters are covered by production test and guaranteed over operating temperature range.
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26V Storage Temperature Range . . . . . -65C to +150C Power Dissipation (package limitation) Ceramic package . . . . . . . . . . . . . . . . . . . . . . . 750mW Derate above +25C . . . . . . . . . . . . . . . . . . 6mW/C Plastic package . . . . . . . . . . . . . . . . . . . . . . . . . Derate above +25C . . . . . . . . . . . . . . . . . . SOIC package . . . . . . . . . . . . . . . . . . . . . . . . . Derate above +25C . . . . . . . . . . . . . . . . . 625mW 5mW/C 500mW 4mW/C
Rev. 2.02 4
XR-2207
VCC
Q1 Q2
Q3 Q4
1
Q14 Q13
Q15
2R
Q5 R Q19 R1 Q6 Q7 Q8 R Timing Capacitor 2 3 Q9 Q10 Q11 Q12 R3
R R
- + 2R
14
Triangle Wave Output
R2
4R 7 6 5 4 Q18
R4
Timing Resistors Q16 9 Q17 Binary Keying Inputs B 8 A A B
Square Wave Output R5 Q20 R6 Q21 Q27 R7 13
10 Ground 11 BIAS Q23
Q22
Q24
Q25 Q26
VEE 12
Figure 2. Equivalent Schematic Diagram
Rev. 2.02 5
XR-2207
PRECAUTIONS The following precautions should be observed when operating the XR-2207 family of integrated circuits: 1. Pulling excessive current from the timing terminals will adversely affect the temperature stability of the circuit. To minimize this disturbance, it is recommended that the total current drawn from pins 4, 5, 6, and 7 be limited to 6mA. In addition, permanent damage to the device may occur if the total timing current exceeds 10mA. 2. Terminals 2, 3, 4, 5, 6 , and 7 have very low internal impedance and should, therefore, be protected from accidental shorting to ground or the supply voltage. 3. The keying logic pulse amplitude should not exceed the supply voltage. SYSTEM DESCRIPTION The XR-2207 functional blocks are shown in the block diagram given in Figure 1. They are a voltage controlled oscillator (VCO), four current switches which are controlled by binary keying inputs, and two buffer amplifiers for triangle and squarewave outputs. Figure 2 is a simplified XR-2207 schematic diagram that shows the circuit in greater detail. The VCO is a modified emitter-coupled current controlled multivibrator. Its oscillation is inversely proportional to the value of the timing capacitor connected to pins 2 and 3, and directly proportional to the total timing current IT. This current is determined by the resistors that are connected from the four timing terminals (pins 4, 5, 6 and 7) to ground, and by the logic levels that are applied to the two binary keying input terminals (pins 8 and 9). Four different oscillation frequencies are possible since IT can have four different values. The triangle output buffer has a low impedance output (10 TYP) while the squarewave is an open-collector type. An external bias input allows the XR-2207 to be used in either single or split supply applications.
VCC VCC I+ 0.1F 1 2 V+ C1 Binary Keying Inputs 0.1F 8 9 10 A B GND R1 R 2 R 3 R4 V4 5 6 7 12 R1 R2 R3 R4 3.9K 3 C2 C RL 13 14 11 BIAS 5.1K Square Wave Output Triangle Wave Output VCC S2
SWO TWO
XR-2207
S1
Figure 3. Test Circuit for Single Supply Operation
Rev. 2.02 6
XR-2207
VCC I+ 0.1F 1 8 Binary Keying Inputs 9 10 V+ A B GND 2 C1 3 C2 13 14 11 C RL Square Wave Output Triangle Wave Output VCC S2
SWO TWO BIAS
XR-2207
R1 R2 R3 R4 V4 5 6 7 12 R1 R2 R3 R4
IVEE 0.1F
S1
Figure 4. Test Circuit for Split Supply Operation
OPERATING CONSIDERATIONS Supply Voltage (Pins 1 and 12) The XR-2207 is designed to operate over a power supply range of $4V to $13V for split supplies, or 8V to 26V for single supplies. Figure 5 shows the permissible supply voltage for operation with unequal split supply voltages. Figure 6 and Figure 7 show supply current versus supply voltage Performance is optimum for $6V split supply, or 12V single supply operation. At higher supply voltages, the frequency sweep range is reduced. Ground (Pin 10) For split supply operation, this pin serves as circuit ground. For single supply operation, pin 10 should be AC grounded through a 1F bypass capacitor. During split supply operation, a ground current of 2IT flows out of this terminal, where IT is the total timing current. Bias for Single Supply (Pin 11) For single supply operation, pin 11 should be externally biased to a potential between V+/3 and V+/2V (see Figure 3). The bias current at pin 11 is nominally 5% of the total oscillation timing current, IT.
Rev. 2.02 7
Bypass Capacitors The recommended value for bypass capacitors is 1F although larger values are required for very low frequency operation. Timing Resistors (Pins 4, 5, 6, and 7) The timing resistors determine the total timing current, IT, available to charge the timing capacitor. Values for timing resistors can range from 2k to 2M; however, for optimum temperature and power supply stability, recommended values are 4k to 200k (see Figure 8, Figure 9, Figure 10 and Figure 11). To avoid parasitic pick up, timing resistor leads should be kept as short as possible. For noisy environments, unused or deactivated timing terminals should be bypassed to ground through 0.1F capacitors. Timing Capacitor (Pins 2 and 3) The oscillator frequency is inversely proportional to the timing capacitor, C. The minimum capacitance value is limited by stray capacitances and the maximum value by physical size and leakage current considerations. Recommended values range from 100pF to 100F. The capacitor should be non-polarized.
XR-2207
25 20 Positive Supply (mA) Positive Supply 25 20 RT=2k 15 10 RT=20k 5 0 $4 -5 -10 -15 -20 8 10 12 14 16 18 20 22 24 26 28 Single Supply Voltage (V) Negative Supply (V) $6 $8 RT=200k RT=2Mk RT=3k 35 30 RT=Parallel Combination of Activated Timing Resistors TA=25C
15
10
Typical Operating Range
RT=5k
5 0
$10
$12
$14
Figure 5. Operating Range for Unequal Split Supply Voltages
Figure 6. Positive Supply Current, 1+ (Measured at Pin 1) vs. Supply Voltage
15 Negative Supply Current (mA) TA=25C Total Timing Resistor RT 1M
TA=25C
10
100k
5
10k
Timing Resistor Range
1k 0
0 0
$4V
$8V
$12V
$6
$8
$10
$12
$14 0 8 16 24 Single Supply Voltage (V)
Split Supply Voltage (V)
Figure 7. Negative Supply Current, I(Measured at Pin 12) vs. Supply Voltage
Figure 8. Recommended Timing Resistor Value vs. Power Supply Voltage
Rev. 2.02 8
XR-2207
7 6 5 4 3 2 1 0 -1 -2 -3 -4 -5 -6 -7 1K 10K Normalized Frequency Drift Frequency Error (%) VS=$6V C=5000pF 1.04 1.02 1.00 .98 .96 .94 RT=2M RT=20k RT=200k
100K
1M
10M
.92 $2
TA=25C RT=Total Timing Resistance C=5000pF $4
RT=2k
Timing Resistance () 4 8
$6 $8 $10 $12 Split Supply Voltage (V) 12 16 20 24 Single Supply Voltage (V)
$14
28
Figure 9. Frequency Accuracy vs. Timing Resistance
Figure 10. Frequency Drift vs. Supply Voltage
+2% Normalized Frequency Drift (%)
VS=$6V C=5000pF
4k 2k 200k
2M
+1% 0
20k
20k
4k
-1%
200k
-2%
R=2k 2M
-3%
-50
-25
0
+25 +50 +75 +100 +125
Temperature (C)
Figure 11. Normalized Frequency Drift with Temperature
Rev. 2.02 9
XR-2207
Binary Keying Inputs (Pins 8 and 9) The logic levels applied to the two binary keying inputs allow the selection of four different oscillator frequencies. The internal impedance at these pins is approximately 5k. Keying voltages, which are referenced to pin 10, are < 1.4 V for "zero" and > 3V for "one" logic levels. Table 1 relates binary keying input logic levels, and selected timing pins to oscillator output frequency for each of the four possible cases.
Timing Capacitor C 2 IT/2 3 IT/2 VCC 1 Ib
T4 T3 T2 T1 A 8 B
10
Figure 12 shows the oscillator control mechanism in greater detail. Timing pins 4, 5, 6 and 7 correspond to the emitters of switching transistor pairs T1, T2, T3, and T4 respectively, which are internal to the integrated circuit. The current switches, and corresponding timing terminals, are activated by external logic signals applied to pins 8 and 9.
Logic Level Pin 8 0 0 1 1 Pin 9 0 1 0 1 Selected Timing Pins 6 6 and 7 5 4 and 5 Frequency f1 f1 + Df1 f2 f2 + Df2
Binary Keying Controls I1
9
4
5 I2
6 I3
7 I4
V
R1 R2 R3 R4 12 VEE
Figure 12. Simplified Schematic of Frequency Control Mechanism Squarewave Output (Pin 13) The squarewave output at pin 13 is an "open-collector" stage capable of sinking up to 20mA of load current. RL serves as a pull-up load resistor for this output. Recommended values for RL range from 1k to 100k. Triangle Output (Pin 14) The output at pin 14 is a triangle wave with a peak swing of approximately one-half of the total supply voltage. Pin 14 has a 10 output impedance and is internally protected against short circuits. MODES OF OPERATION Split Supply Operation
Table 1. Logic Table for Binary Keying Controls
Definitions:
f1 + 1 Df1 + 1 Df2 + 1 Df2 + 1 R3C R4C R2C R1C
Logic Levels: 0 = Ground, 1 3V
Note For single supply operation, logic levels voltage at pin 10 are referenced to
Figure 13 is the recommended configuration for split supply operation. The circuit operates with supply voltages ranging from $4V to $13V. Minimum drift occurs with $6V supplies. For operation with unequal supply voltages, see Figure 5.
With the generalized circuit of Figure 13A, the frequency of operation is determined by the timing capacitor, C, and the activated timing resistors (R1 through R4). The timing resistors are activated by the logic signals at the binary
Rev. 2.02 10
XR-2207
keying inputs (pins 8 and 9), as shown in the logic table (Table 1). If a single timing resistor is activated, the frequency is 1/RC. Otherwise, the frequency is either 1/(R1||R2)C or 1/(R3||R4)C. peak-to-peak voltage swing equal to the supply voltages. This output is an "open-collector" type and requires an external pull-up load resistor (nominally 5k) to the positive supply. The triangle waveform obtained at pin 14 is centered about ground and has a peak amplitude of V+/2.
Note For Single-Supply Operation, Logic Levels are referenced to voltage at Pin 10.
VCC VCC 1 8 Keying Inputs 9 V+ C1 A B 2 C2 SWO TWO BIAS 11 C RL 3 13 14 Square Wave Output Triangle Wave Output
Figure 13B shows a fixed frequency application using a single timing resistor that is selected by grounding the binary keying inputs. The oscillator frequency is 1/R3C.
The squarewave output is obtained at pin 13 and has a
CB
XR-2207
10 GND
R 1 R 2 R 3 R 4 V456 7 12 R1 R2 R3 R4 VEE CB = Bypass Cap CB
VEE
A. General Case
CB VCC 1 8 9 10 V+ C 1 A B GND 2 C
VCC
RL 3 C2 SWO TWO BIAS R 1 R 2 R 3 R4 V456 7 12 R3 CB = Bypass Cap VEE CB 13 14 11 Square Wave Output Triangle Wave Output f=1/R3XR-2207
VEE
B. Fixed Frequency Case Figure 13. Split-Supply Operation
Rev. 2.02 11
XR-2207
Single Supply Operation The circuit should be interconnected as shown in Figure 14A or Figure 14B for single supply operation. Pin 12 should be grounded, and pin 11 biased from VCC through a resistive divider to a value of bias voltage between V+/3 and V+/2. Pin 10 is bypassed to ground through a 1F capacitor. For single supply operation, the DC voltage at pin 10 and the timing terminals (pins 4 through 7) are equal and approximately 0.6V above VB, the bias voltage at pin 11. The logic levels at the binary keying terminals are referenced to the voltage at pin 10.
VCC CB VCC C RL 1 8 Keying Inputs CB 10 9 V+ A B GND 2 C1 3 C2 SWO TWO BIAS R 1 R 2 R 3 R 4 V4 5 6 7 12 CB = Bypass Cap R1 R2 R3 R4 13 14 11 Square Wave Output Triangle Wave Output VCC 5.1K 3.9K
XR-2207
A. General Case
CB VCC C
VCC
RL 1 V+ 8 9 10 A B GND 2 C1 3 C2 SWO TWO BIAS R 1 R 2 R 3 R 4 V4 5 6 7 12 R3 f=1/R313 14 11
XR-2207
CB
B. Single Frequency Figure 14. Single Supply Operation
Rev. 2.02 12
XR-2207
Frequency Control (Sweep and FM) The frequency of operation is controlled by varying the total timing current, IT, drawn from the activated timing pins 4, 5, 6, or 7. The timing current can be modulated by applying a control voltage, VC, to the activated timing pin through a series resistor RC. As the control voltage becomes more negative, both the total timing current, IT, and the oscillation frequency increase. The circuits given in Figure 15 and Figure 16 show two different frequency sweep methods for split supply operation. Both binary keying inputs are grounded for the circuit in Figure 15. Therefore, only timing pin 6 is activated. The circuit of Figure 15 can operate both with positive and negative values of control voltage. However, for positive values of VC with small (RC/R3) ratio, the direction of the timing current IT is reversed and the oscillations will stop.
Figure 16 shows an alternate circuit for frequency control where two timing pins, 6 and 7, are activated. The frequency and the conversion gain expressions are the same as before, except that the circuit will operate only with negative values of VC. For VC > 0, pin 7 becomes deactivated and the frequency is fixed at: f+ 1 R3
The circuit given in Figure 17 shows the frequency sweep method for single supply operation. Here, the oscillation frequency is given as:
f+ 1 The frequency of operation, normally R3C is now proportional to the control voltage, VC, and determined as: f+ 1 R3C
1 * VCR3 Hz RCV-
f+ 1 R3C
1 ) R3 1 * VC RC VT
where VT = Vbias + 0.7V. If R3 = 2M, RC = 2k, C = 5000pF, then a 1000:1 frequency sweep would result for a negative sweep voltage VC V-. The voltage to frequency conversion gain, K, is controlled by the series resistance RC and can be expressed as: This equation is valid from VC = 0V (RC is in parallel with R3) to
VC + VT 1 ) RC R3
Caution Total timing current IT must be less than 6mA over the frequency control range.
K + Df + 1 Hz V DVC RCCV-
Rev. 2.02 13
XR-2207
VCC CB VCC C 4.7K 12 V+ C1 A B GND R1 R2 R3 R4 V4 5 6 7 12 IT IO CB = Bypass Cap R3 RC IC 3 C2 SWO TWO BIAS 13 14 11 Square Wave Output Triangle Wave Output
8 9
f + 1 1 * VCR3 RCVCR3
XR-2207
10
VEE CB
VEE VC
VC
Sweep or FM input
Figure 15. Frequency Sweep Operation, Split Supply
VCC CB VCC C 4.7K 1 8 V+ A B GND R1 R2 R3 R4 V4 567 12 VEE IO CB = Bypass Cap R3 RC IC CB 2 C1 3 C2 13 14 Square Wave Output Triangle Wave Output
SWO TWO
f + 1 1 * VCR3 RCVCR3
VCC
9 10
XR-2207
BIAS 11
VEE VC
VC
Sweep or FM input
Figure 16. Alternate Frequency Sweep Operation, Split Supply
Rev. 2.02 14
XR-2207
VCC 1F 1 2 V+ C1 8A C 4.7K 3 13 C2 SWO 14 TWO XR-2207 11 BIAS VCC
Square Wave Output Triangle Wave Output
f + 1 1 ) R3 1 * VC RC VT CR3
9
B
Vbias 5.1K 1F 3.9K
10 GND
VCC
R1 R2 R3 R4 V4 5 6 7 12 1F VT 1F
VEE
RC
R3
VCVC
VC+
Sweep or FM input
Figure 17. Frequency Sweep Operation, Single Supply
Duty Cycle Control
The duty cycle of the output waveforms can be controlled by frequency shift keying at the end of every half cycle of oscillator output. This is accomplished by connecting one or both of the binary keying inputs (pins 8 or 9) to the squarewave output at pin 13. The output waveforms can then be converted to positive or negative pulses and sawtooth waveforms.
Duty Cycle +
R2 R2 ) R3
and can be varied from 0.1% to 99.9% by proper choice of timing resistors. The frequency of oscillation, f, is given as: 1 f+2 C R2 ) R3 The frequency can be modulated or swept without changing the duty cycle by connecting R2 and R3 to a common control voltage VC, instead of VEE (see Figure 15). The sawtooth and the pulse output waveforms are shown in Figure 19.
Figure 18 is the recommended circuit connection for duty cycle control. Pin 8 is shorted to pin 13 so that the circuit switches between the "0,0" and the "1,0" logic states given in Table 1. Timing pin 5 is activated when the output is "high," and the timing pin is activated when the squarewave output goes to a low state.
The duty cycle of the output waveforms is given as:
Rev. 2.02 15
XR-2207
4.7K VCC VCC CB C
1 8 9 10 V+ A B GND R1 4 R2 C1
2 C2
3 SWO 13 14 11 Sawtooth Output Pulse Output
XR-2207
TWO BIAS
R2 5
R3 6
R4 7
V12 VEE CB CB = Bypass Cap
R3
VEE
Figure 18. Duty Cycle Control
Rev. 2.02 16
XR-2207
On-Off Keying
The XR-2207 can be keyed on and off by simply activating an open circuited timing pin. Under certain conditions, the circuit may exhibit very low frequency (<1Hz) residual oscillations in the "off" state due to internal bias currents. If this effect is undesirable, it can be eliminated by connecting a 10M resistor from pin 3 to VCC.
A. Squarewave and Triangle Outputs
Two-Channel FSK Generator (Modem Transmitter)
The multi-level frequency shift-keying capability of XR-2207 makes it ideally suited for two-channel FSK generation. A recommended circuit connection for this application is shown in Figure 20. For two-channel FSK generation, the "mark" and "space" frequencies of the respective channels are determined by the timing resistor pairs (R1, R2) and (R3, R4). Pin 8 is the "channel-select" control in accord with Figure 11. For a "high" logic level at pin 8, the timing resistors R1 and R2 are activated. Similarly, for a "low" logic level, timing resistors R3 and R4 are enabled. The "high" and "low" logic levels at pin 9 determine the respective high and low frequencies within the selected FSK channel. When only a single FSK channel is used, the remaining channel can be deactivated by connecting pin 8 to either VCC or ground. In this case, the unused timing resistors can also be omitted from the circuit. The low and high frequencies, f1 and f2, for a given FSK channel can be fine tuned using potentiometers connected in series with respective timing resistors. In fine tuning the frequencies, f1 should be set first with the logic level at pin 9 in a "low" level. Typical frequency drift of the circuit for 0C to 75C operation is $0.2%. Since the frequency stability is directly related to the external timing components, care must be taken to use timing components with low temperature coefficients.
B. Pulse and Sawtooth Outputs
C. Frequency Shift Keyed Outputs
Figure 19. Output Waveforms
Rev. 2.02 17
XR-2207
VCC VCC C 1F RL 1 2 V+ C1 Channel Select 3V OV f2 f1 Keying Input 8 9 10 A B GND R1 4 R1 R2 R2 5 R3 R3 R4 6 R4 7 V12 3 C2 SWO
13 14 11 f1 f2
FSK Output
XR-2207
TWO BIAS
1F 10K 10K 10K 10K
VEE
Figure 20. Multi-Channel FSK Generation
Rev. 2.02 18
XR-2207
14 LEAD CERAMIC DUAL-IN-LINE (300 MIL CDIP)
Rev. 1.00
14
8
1
7
E D Base Plane Seating Plane L e B B1 c A1 A E1
INCHES SYMBOL A A1 B B1 c D E1 E e L MIN 0.100 0.015 0.014 0.045 0.008 0.685 0.250 MAX 0.200 0.060 0.026 0.065 0.018 0.785 0.310
MILLIMETERS MIN 2.54 0.38 0.36 1.14 0.20 17.40 6.35 MAX 5.08 1.52 0.66 1.65 0.46 19.94 7.87
0.300 BSC 0.100 BSC 0.125 0.200
7.62 BSC 2.54 BSC 3.18 5.08 15
0 15 0 Note: The control dimension is the inch column
Rev. 2.02 19
XR-2207
14 LEAD PLASTIC DUAL-IN-LINE (300 MIL PDIP)
Rev. 1.00
14 1 D
8 7 E1 E A2
Seating Plane
A L A1 B e B1
eA eB
C
INCHES SYMBOL A A1 A2 B B1 C D E E1 e eA eB L MIN 0.145 0.015 0.115 0.014 0.030 0.008 0.725 0.300 0.240 MAX 0.210 0.070 0.195 0.024 0.070 0.014 0.795 0.325 0.280
MILLIMETERS MIN 3.68 0.38 2.92 0.36 0.76 0.20 18.42 7.62 6.10 MAX 5.33 1.78 4.95 0.56 1.78 0.38 20.19 8.26 7.11
0.100 BSC 0.300 BSC 0.310 0.115 0 0.430 0.160 15
2.54 BSC 7.62 BSC 7.87 2.92 0 10.92 4.06 15
Note: The control dimension is the inch column
Rev. 2.02 20
XR-2207
16 LEAD SMALL OUTLINE (300 MIL JEDEC SOIC)
Rev. 1.00
D
16
9
E
1 8
H
C Seating Plane e B A1 L A
INCHES SYMBOL A A1 B C D E e H L MIN 0.093 0.004 0.013 0.009 0.398 0.291 MAX 0.104 0.012 0.020 0.013 0.413 0.299
MILLIMETERS MIN 2.35 0.10 0.33 0.23 10.10 7.40 MAX 2.65 0.30 0.51 0.32 10.50 7.60
0.050 BSC 0.394 0.016 0 0.419 0.050 8
1.27 BSC 10.00 0.40 0 10.65 1.27 8
Note: The control dimension is the millimeter column
Rev. 2.02 21
XR-2207 Notes
Rev. 2.02 22
XR-2207 Notes
Rev. 2.02 23
XR-2207
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1975 EXAR Corporation Datasheet June 1997 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 2.02 24

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